Lightly doped drain (LDD) structures are implemented in the substrate of NMOSFET and PMOSFET devices to reduce the MOSFET's short channel effect (SCE), hot carrier effect (HCE) and gate induced drain leakage (GIDL). A spacer is used to allow formation of a desired length of the LDD region below the spacer.
The LDD spacer length requirement for NMOSFET and PMOSFET devices are different. For NMOS devices, the LDD spacer length should be as short as possible to reduce the series resistance of the LDD region. This provides for optimum HCE, SCE and GIDL effects for an NMOS device.
PMOS devices have a larger lateral diffusion from the P.sup.+ source/drain regions than the lateral diffusion of N.sup.+ source/drain regions of NMOS devices. To counteract this larger lateral diffusion and to reduce the SCE, HCE, and GIDL effects in a PMOS device, the length of the LDD region of the PMOS device is preferably larger than that of the NMOS device. Therefore, using a similar length LDD spacer for both NMOS and PMOS devices does not result in an optimum reduction of the SCE, HCE, and GIDL effects for both the NMOS and PMOS devices.
FIGS. 1(A)-1(E) illustrate a first prior art process for making a semiconductor device having an LDD structure. This first prior art process uses only one type of spacer for a semiconductor structure 100 having an NMOS device 102 and a PMOS device 104 formed in a substrate 110. The substrate 110 may be N-type or P-type. In step (A) shown in FIG. 1(A), a P-well 115 and an N-well 120 are formed in the substrate 110. A thin gate oxide layer 125 is formed on the wells 115, 120 by thermal oxidation of the surface of the wells 115, 120. Thicker field oxide regions 130 are used to separate adjacent devices. One of the field oxide regions 130 is formed at the boundary of the P-well 115 and the N-well 120. The polysilicon gates 135 are formed on the gate oxide 125.
In step (B) shown in FIG. 1(B), a polysilicon oxide 140 is formed over the polysilicon gates 135. N-type impurities are implanted in the P-well 115 to form N.sup.- regions 145. Similarly, P-type impurities are implanted in the N-well 120 to form P.sup.- regions 150. The regions 145, 150 are formed between the field oxide regions 130 and the polysilicon oxide layer 140 covering the polysilicon gates 135.
In step (C) shown in FIG. 1(C), an oxide or a nitride layer 155 is deposited on the entire semiconductor structure 100 covering the gates 135 of the NMOS and PMOS devices 102, 104.
In step (D) shown in FIG. 1(D), anisotropic etching of the oxide or nitride layer 155 (shown in FIG. 1(C)) is performed to form oxide or nitride spacers 160 of a desired length L on the side walls of the gates 135.
In step (E) shown in FIG. 1(E), N-type impurities are implanted in the P-well 115 only by first masking the PMOS device 104 with a photoresist layer (not shown). The implanted N-type impurities form N.sup.+ source/drain regions 175 in a portion of the N.sup.+ regions 145 (see FIG. 1(D)). Similarly, P-type impurities are implanted only in the N-well 120 after removing the photoresist layer covering the PMOS device 104 and masking the NMOS device 102 with another photoresist layer (not shown). The implanted P-type impurities form P.sup.+ source/drain regions 180 in a portion of the P.sup.- regions 150 (see FIG. 1(D)). The source/drain regions 175, 180 are formed between the field oxide regions 130 and the edge of the spacers 160 farthest away from the gates 135.
The portions of the N.sup.- and P.sup.- regions 145, 150 (shown in FIG. 1(D)) remaining below the spacers 160 are the LDD regions 185, 190 of the NMOS and PMOS devices 102, 104 respectively. The LDD regions 185, 190 are defined by the length L of the spacer 160. Therefore, the N-LDD and P-LDD regions 185, 190 have the same length which equals to the length L of the spacer 160.
Finally, conventional back end processes are performed such as an interlayer-dielectric (ILD) deposition, ILD planarization, contact opening, metal deposition, metal pattern definition and passivation.
This conventional LDD process only uses one kind of spacer 160 having the same length L. Thus, the LDD regions 185, 190 of both the NMOS and PMOS devices 102, 104 have the same length L. Because of differing optimal LDD region lengths for NMOS and PMOS devices, the NMOS and PMOS devices 102, 104 preferably should not both have LDD regions of the same length. Thus, the semiconductor structure 100 formed with this process cannot have an optimal length for both the N-LDD 185 and an P-LDD 190 regions. Therefore, the semiconductor structure 100 formed with this process cannot have NMOS and PMOS devices 102, 104 which are both optimized for device characteristics.
To optimize both the NMOS and PMOS characteristics, different LDD spacer lengths are required. There are two conventional ways to optimize the characteristics of both NMOS and PMOS devices of a semiconductor. One method is described in U.S. Pat. No. 5,278,441 (Kang) and U.S. Pat. No. 5,254,866 (Ogoh).
FIGS. 2(A)-2(G) illustrate a second prior art process that uses two spacers for a semiconductor structure 200 having an NMOS 202 device and a PMOS 204 device. The initial steps in the formation of the semiconductor structure 200 are identical to steps (A) to (D) of FIGS. 1(A)-1(D). FIG. 2(D) shows a first spacer 260 formed around polysilicon gates 235. The first spacer 260 is analogous to the spacer 160 of FIG. 1(D) and is formed using steps similar to steps (A) to (D) of FIGS. 1(A)-1(D).
In step (A) shown in FIG. 2(A), a P-well 215 and an N-well 220 are formed in a substrate 210 which may be N-type or P-type. A thin gate oxide layer 225 is formed on the wells 215, 220 by thermal oxidation of the surface of the wells 215, 220. Thicker field oxide regions 230 are used to separate adjacent devices. One of the field oxide regions 230 is formed at the boundary of the P-well 215 and the N-well 220. The polysilicon gates 235 are formed on the gate oxide 225.
In step (B) shown in FIG. 2(B), a polysilicon oxide 240 is formed over the polysilicon gates 235. N-type impurities are implanted in the P-well 215 to form N.sup.- regions 245. Similarly, P-type impurities are implanted in the N-well 220 to form P.sup.- regions 250. The regions 245, 250 are formed between the field oxide regions 230 and the polysilicon oxide layer 240 covering the polysilicon gates 235.
In step (C) shown in FIG. 2(C), an oxide or a nitride layer 255 is deposited on the entire semiconductor structure 200 covering the gates 235 of the NMOS and PMOS devices 202, 204.
In step (D) shown in FIG. 2(D), anisotropic etching of the oxide or nitride layer 255 (shown in FIG. 2(C)) is performed to form oxide or nitride spacers 260 of a desired length L on the side walls of the gates 235.
In step (E) shown in FIG. 2(E), N-type impurities are implanted in the P-well 215 only by first masking the PMOS device 204 with a photoresist layer 262. The implanted impurities form N.sup.+ source/drain regions 275 in a portion of the N.sup.- regions 245 (shown in FIG. 2(D)).
In step (F) shown in FIG. 2(F), after removing the photoresist layer 262 covering the PMOS device 204, a second spacer 265 is formed in a similar fashion as the first spacer 260. That is, a second oxide or a nitride layer (not shown) is deposited on the entire semiconductor structure 200, including the first spacers 260. This second layer is anisotropically etched to form the second spacers 265 of a desired length L.sub.2 on the first spacers 260.
In step (G) shown in FIG. 2(G), P-type impurities are implanted in the N-well 220 only by first masking the NMOS device 202 by a photoresist layer 277. The implanted impurities form P.sup.+ source/drain regions 280 in a portion of the P.sup.- regions 250 (shown in FIG. 2(F)). The effective spacer length L.sub.eff during the formation of the P+source/drain regions 280 for the PMOS 204, equals the length L.sub.1 of the first spacer 260 plus the length L.sub.2 of second spacer 265; i.e., L.sub.eff =L.sub.1 +L.sub.2.
The portions of the N.sup.- regions 245 (shown in FIG. 2(D)) remaining below the spacers 260 are the N-LDD regions 285 of the NMOS device 202. The portions of the P.sup.- regions 250 (shown in FIG. 2(D)) remaining below the spacers 260, 265 are the P-LDD regions 290 of the PMOS devices 204. The LDD regions 285, 290 are defined by the lengths of the spacers 360, 365. Therefore, the length of the N-LDD regions 285 are nearly equal to the length L.sub.1 of the spacer 260, and the length of the P-LDD regions 290 equals to the combined length L.sub.eff of the two spacers 260, 265.
Finally, the photoresist layer 277 is removed and back end process steps similar to the back end steps described in connection with FIGS. 1(A)-1(E) are performed.
In this fashion, the spacers used for forming the P.sup.+ source/drain regions 280 of the PMOS device 204 have a length L.sub.eff which is longer than the length L.sub.1 of the first spacer 260 used for forming N.sup.+ source/drain regions 275 of the NMOS device 202. These lengths L.sub.1 and L.sub.eff can be chosen independently to form the LDD regions 285, 290 with desired lengths which are independent of each other. Thus, the characteristics of both the NMOS and PMOS devices 202, 204 of the semiconductor structure 200 can be optimized.
However, this method has many disadvantages. It requires an additional LDD spacer formation step thus requiring two anisotropic etching steps. For oxide spacers, the two anisotropic etching steps will substantially reduce the thickness of the field oxide regions 320. This results in a reduced field isolation. Furthermore, the two anisotropic etching steps will substantially etch away the edges of the field oxide regions 230. This induces junction leakage at the edges of the field oxide regions 230.
A second conventional method for optimizing the NMOS and PMOS characteristics of a semiconductor is disclosed in U.S. Pat. No. 5,270,233 (Hamatake) and U.S. Pat. No. 5,134,085 (Gilgen). As shown in FIGS. 3(A)-(E), in this second conventional method, the NMOS and PMOS devices 302, 304 of a semiconductor structure 300 are formed sequentially. That is, after completely forming one device (e.g., the NMOS device 302), the other device (e.g., the PMOS device 304) is formed.
In step (A) shown in FIG. 3(A), a P-well 315 and an N-well 320 are formed in a substrate 310 which may be N-type or P-type. A thin gate oxide layer 325 is formed on the wells 315, 320 by thermal oxidation of the surface of the wells 315, 320. Thicker field oxide regions 330 are used to separate a adjacent devices. One of the field oxide regions 330 is formed at the boundary of the P-well 215 and the N-well 220. The polysilicon gates 335 are formed on the gate oxide 325. Then, a polysilicon oxide 336 is formed over the polysilicon gates 335.
In step (B) shown in FIG. 3(B), using, for example, a photoresist layer 337 as a mask to cover the PMOS device 304, N-type impurities are implanted in the P-well 315 to form N.sup.- regions 345. Then an oxide layer 340 is formed over the polysilicon gate 335 of the NMOS device 302. In Hamatake, silicon dioxide is formed over the gate 335 of the NMOS device 302 using a liquid phase deposition (LPD) method. Because there is the photoresist layer 337 covering the PMOS device 304, the oxide layer 340 is not formed over the PMOS device 304.
In step (C) shown in FIG. 3(C), spacers 360 of a desired length L.sub.1 are formed on the side walls of the gate 335 of the NMOS 302. The spacers 360 are formed from the oxide layer 340 in a similar fashion as the spacers 360 of FIG. 2(D).
In step (D) shown in FIG. 3(D), N-type impurities are implanted in the P-well 315. The implanted impurities form N.sup.+ source/drain regions 375 in a portion of the N.sup.- regions 345 (shown in FIG. 3(C)).
In step (E) shown in FIG. 3(E), the photoresist layer 337 from the PMOS device 304 is removed and steps similar to steps FIGS. 3(B) to 3(D) are repeated. That is, the NMOS device 302 is covered with a photoresist layer 377; P-type impurities are implanted in the N-well 320 to form P.sup.- regions (not shown) which are similar to the N.sup.- regions 345 shown in FIG. 3(B); an oxide layer (not shown), which is similar to the oxide layer 340 shown in FIG. 3(B), is formed over the polysilicon gate 335 of the PMOS device 304; spacers 365 of a desired length L.sub.2 are formed on the side walls of the gates 335 from the oxide layer (not shown); and P-type impurities are implanted in the N-well 320 to form P.sup.+ source/drain regions 380 in a portion of the P.sup.- regions (not shown). Finally, the photoresist layer 377 is removed and similar back end processes are performed as the previous methods.
As shown in FIG. 3(E), the portions of the N.sup.- regions 345 (shown in FIG. 3(C)) remaining below the spacers 360 are the N-LDD regions 385 of the NMOS device 302. The portions of the P.sup.- regions (not shown) remaining below the spacers 360, 365 are the P-LDD regions 390 of the PMOS devices 304. The lengths L.sub.1, L.sub.2 of the LDD regions 385, 390 are nearly equal to the lengths of the spacers 360, 365 respectively. That is, the LDD regions 385, 390 are defined by the lengths of the spacers 360, 365 respectively.
Although this process allows formation of LDD regions 385, 390 that have independently determined lengths L.sub.1 and L.sub.2, this process has many disadvantages. This process is complex and requires an additional spacer deposition and etching. Furthermore, the NMOS and PMOS devices 302, 304 must be separately formed, e.g., sequentially. In addition, the process disclosed by Hamatake, requires the spacer oxide layer to be grown over the gate 335 of the NMOS device 302 and the PMOS device 304 using an LPD method.
It is therefore an object of the present invention to overcome the disadvantages of the prior art.
It is another object of the present invention to make a semiconductor integrated circuit structure having a variable length LDD spacer structure using a simple method.
It is yet another object of the present invention to make a semiconductor integrated circuit structure having a variable length LDD spacer structure by oxidizing polysilicon spacers to increase their size.